This application relates to memory controllers, and in particular, to managing skew in data signals, using multiple modes.
In a typical memory system, a memory and a memory controller connect to a common bus that has several parallel wires. Each wire, which carries one bit, will be referred to herein as a “data line.”
The signal present on each data line represents data. It will therefore be referred to herein as the “data signal.” In a typical memory with eight-bit bytes, there would be eight of these data signals for every byte.
In a typical memory system, the wires that carry a byte include data lines, with one data line for each bit. Thus, for an eight-bit byte, there would be eight data lines. However, there is also an extra pair of wires. This extra wire pair carries a differential signal that functions as a reference clock for sampling the data lines. The differential signal carried by these extra wires is often called a “strobe” or a “timing signal.” The wires that carry this timing signal are collectively called a “strobe line.”
For example, such a memory system may include a memory controller for a memory module that includes a number of synchronous dynamic random access (SDRAM) memory chips. In such a system the data line may be called a “DQ” signal, and the strobe may be called a “DQS” signal.
In the process of writing to the memory, a memory controller receives several n-bit units worth of data, together with an instruction to write those units into the memory. Each unit has n data bits and an associated strobe line. For each n-bit unit, the controller places each of the n bits on each of the n individual data lines corresponding to those n bits. As part of this task, the memory controller places a strobe on the strobe line for each n-bit unit. For each n-bit unit, the memory makes use of the strobe to sample the data lines for that unit, and stores the corresponding data into the memory array. In some embodiments, n=8. However, in other embodiments n=4.
The data lines may be bidirectional. So, in the process of reading from the memory, the controller issues one or more commands to the memory. In response, the memory places data signals on the data lines and a corresponding strobe on the strobe line. The controller then retrieves the data from the bidirectional data lines.
In the ideal case, the timing of the strobe and the data signals should be maintained with a particular relative phase offset while propagating between the controller and the memory. However, in practice, different data lines have different skews in the data signals. These different skews, which result in different relative phase offsets, arise as a result of variations in the path-lengths of the routes followed by the data signals as they traverse the package that contains a memory component, a module containing multiple packaged memory components, a printed circuit board that connects the controller to the memory module, and the package of the memory controller. For example, temperature may also cause such variations. As a result of higher data rates, the effects of these variations are more significant.